F71862
0: reserved.
1: fan3 follow temperature 1.
2: fan3 follow temperature 2.
3: fan3 follow temperature 3.
1-0
Fan3_temp_sel
R/W
3h
7.7 SPI Interface
Communication between the two devices is handling the serial peripheral interface
(SPI). Every SPI system consist of one master and one or more slaves, where a master
provides the SPI clock and slave receives clock from the master.
This design is only master function, for basic signal, master-out/slave-in (MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for
SPI interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by
configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5
KHz. The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or
falling edge is decided by configuration register.
7.8 ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the
use of power in a computer. It lets computer manufacturer and user to determine the
computer’s power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they
are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in
this state. The other two are called sleep states and reflect different power consumption when
power-down. S3 is a state that the processor is powered down but the last procedural state is
being stored in memory which is still active. S5 is a state that memory is off and the last
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as
comparison, since memory is fast, the computer can quickly come back to full-power state, the
disk is slower than the memory and the computer takes longer time to come back to full-power
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is
necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only
as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state
transition.
The below diagram described the timing, the always on and always off, keep last state
could be set in control register. In keep last state mode, one register will keep the status of
before power loss. If it is power on before power loss, it will remain power on when power is
resumed, otherwise, if it is power off before power loss, it will remain power off when power is
63
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
