F71862
power supply PS_ON# signal. (Default function)
GPIO31
RSMRST#
I/OOD12t
OD12
General purpose IO.
85
87
VBAT Resume Reset# function, It is power good signal of
VSB, which is delayed 66ms as VSB arrives at 2.3V.
(Default function)
GPIO33
COPEN#
I/OOD12t
INts5v
General purpose IO.
VBAT Case Open Detection #. This pin is connected to a
specially designed low power CMOS flip-flop backed
by the battery for case open state preservation during
power loss.
6.8 VID Controller and Others
Pin No.
Pin Name
Type
PWR
Description
45-42
VIDIN[D:A]
INts5v
VCC
CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
CPU VID output pins.
52-49
VIDOUT[D:A]
OD12
VSB
46
47
53
54
55
GPIO44
GPIO45
GPIO00
GPIO01
ST2
I/OOD12t VCC
I/OOD12t VCC
I/OOD12t VSB
I/OOD12t VSB
General purpose IO.
General purpose IO.
General purpose pin.
General purpose pin.
Status Pin2 for S0#/S3#/S5# states application.
(Default function)
OD12
VSB
In S0# Æ ST2 pin status is Tri-state.
In S3# Æ ST2 pin status is Low level.
In S5# Æ ST2 pin status is Low level, and can be
programmed to Tri-state.
SLOTOCC#
INts5v
CPU SLOTOCC# input.
GPIO02
ST1
I/OOD12t
OD12
General purpose pin.
Status Pin1 for S0#/S3#/S5# states application.
(Default function)
In S0# Æ ST1 pin status is Tri-state.
In S3# Æ ST1 pin status is Low level.
In S5# Æ ST1 pin status is Tri-state.
General purpose pin.
56
VSB
VSB
GPIO03
WDTRST#
I/OOD12t
OD12-5v
Watch dog timer signal output.
57
58
SIC
PECI
OD12
ILv/OD8-S1 VSB
AMDSI interface clock output.
Intel PECI hardware monitor interface. (Default by
register setting)
SID
ILv/OD12
AMDSI interface data input. (Default by register
setting)
6.9 KBC Function
Pin No.
Pin Name
Type
PWR
Description
40
KBRST#
OD16-u10,5V VCC
Keyboard reset. This pin is high after system reset.
16
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
