F71869A
5
4
Reserved
-
-
-
Reserved
0: The Fan Duty is 100% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull
down by external resistor)
FULL_DUTY_SEL R/W
1: The Fan Duty is 40% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull
up by internal 47K resistor).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to cause
fan fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the
fan expect count in time.
The unit of this register is 1 second. The default value is 11 seconds.
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
3-0
F_FAULT_TIME R/W
Ah
Another condition to cause fan fault event is fan stop and the PWM
duty is greater than the minimum duty programmed by the register
index 9C-9Dh.
6.6.65 FAN1 Index A0h~AFh
Address Attribute Default Value
Description
FAN1 count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and followed
read the LSB.
A0h
A1h
RO
RO
8’h0f
8’hff
FAN1 count reading (LSB).
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (MSB), in auto fan mode (CR96
bit1Î0) this register is auto updated by hardware.
Duty mode(CR96 bit0=1):
A2h
R/W
8’h00
This byte is reserved byte.
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (LSB) or expect PWM duty, in auto
fan mode this register is auto updated by hardware and read only.
Duty mode(CR96 bit0=1):
A3h
R/W
8’h01
The Value programming in this byte is duty value. In auto fan mode
(CR96 bit1Î0) this register is updated by hardware.
94
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
