F71869A
00: The OVT# will be low active level mode.
01: The OVT# will be low pulse mode.
5-4
OVT_MODE
R/W
0
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
3
2
Reserved
R/W
R/W
0
0
0: Disable case open event output via PME.
1: Enable case open event output via PME.
CASE_SMI_EN
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
1-0
ALERT_MODE R/W
0
11: The ALERT# will indicate by (400/800HZ) BEEP output.
6.6.7 Configuration Register ⎯ Index 03h
Bit
Name
R/W Default
Description
7-1
Reserved
R/W
R/W
0
1
Reserved
Case open event status. Write 1 to clear if case open event cleared.
(This bit is powered by VBAT.)
0
CASE_STS
6.6.8 NEW TSI Mode Enable Registerꢀ Index 07h
Bit
Name
R/W Default
Description
0
0
7-1
-
Reserved
Reserved
Set this bit to enable TSI new mode. Please check CR0A for more
detail.
0
R/W
New_TSI_MODE
6.6.9 Configuration Register ⎯ Index 08h
Bit Name R/W Default
Description
When AMD TSI or Intel PCH SMBus is enabled, this byte is used as
7-1 SMBUS_ADDR R/W 7’h26 SMBUS_ADDR. SMBUS_ADDR[7:1] is the slave address sent by the
embedded master to fetch the temperature.
0
Reserved
-
-
Reserved
6.6.10
Bit
Configuration Register ⎯ Index 09h
Name
I2C_ADDR
Reserved
R/W Default
Description
I2C_ADDR[7:1] is the slave address sent by the embedded master
when using a block write command
7-1
0
R/W
R/W
0
0
Reserved
72
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
