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F71869AD 参数 Datasheet PDF下载

F71869AD图片预览
型号: F71869AD
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O +硬件监控 [Super I/O + Hardware Monitor]
分类和应用: 监控
文件页数/大小: 156 页 / 1561 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71869A  
S5  
S0  
S3  
S0  
S3  
S5  
S5#  
S3#  
PSON#  
ATXPWGD  
VDDOK_D400  
TIMING_1  
TIMING_2  
TIMING_3  
TIMING_4  
CPU_PWGD  
Figure 15 Timing on/off sequence  
5.5 S3_Gate#, S3P5_Gate# and S0P5_Gate# Timing  
The F71869A provides three additional timing switching pins which are named as S3_Gate#,  
S3P5_Gate# and S0P5_Gate#. They can be applied in the certain applications about power switch  
which depends on the ACPI states. The detail timing can be referred in the following diagrams.  
The default timing of S0P5_Gate# in the S5 state is low, but it can be programmed high by the  
register 0x0AF6.  
39  
Oct., 2011  
V0.19P  
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