F71869A
PCI Reset and PWOK Signals
The F71869A supports 5 output buffers for 5 reset signals.
+3.3V
Delay
LRESET#
Buffer
PCIRST1~5#
PWOK
ATXPG
So far as the PWOK issue is as the figure above. PWOK is delayed 400ms (default) as VCC
arrives 2.8V, and the delay timing can be programmed by register. An additional delay could be
added to PWOK (0ms, 100ms, 200ms and 400ms). If RSTCION# and PCIRST4#/PCIRST5# are
enabled, RSTCON# could be programmed to be asserted via PWROK or PCIRST4#/PCIRST5#.
5.4 Power Timing Control Sequence
The F71869A offers 4 timing pins which are designed for AMD platform power sequence
control including VDIMM, VDDA, Vcore, and VLDT (default) or other timing application
purposes. All the timings on/off are relative to S3#/S5# and can be programmed by the register
0x0AF7. As shown in the below figure, the default timings of TIMING_1~4 are displayed in blue
lines, and all the timings are enabled in the S0 state except TIMING_1. However, TIMING_2~4
can be programmed to enable in the S3 state, and TIMING_1 can also be programmed to
disable in the S3 state, like the dotted blue line shown in the figure below.
VDDOK_D400 is the PWOK delay timing from VDD3VOK. The default setting is that delay
400ms, there are 100ms, 200ms, and 300ms for option. It can be set in the register 0x0AF5.
38
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
