Feature Integration Technology Inc.
Fintek
F15353
H8
m8
3
2
R/W
R/W
-
-
Refer to bit 5.
Day of week data (00 to 06)
W4
A septenary counter. Set it so that it corresponds to the day of the week.
H4
m4
W2
H2
Refer to bit 5.
1
R/W
-
Refer to bit 2
Refer to bit 1.
m2
W1
H1
m1
0
R/W
-
Frequency Mode (INT2ME=0, INT2FE=1)
Bit
Name
R/W Default
Description
Data set in INT1 register_2 is considered as frequency duty data. By setting
each bit from bit[4:0]of the register to “1”, the frequency
corresponding to each bit is selected in an ANDed form. The SC bit
configure a 3-bit SRAM type register that can be set freely by users. These
bits can be read and written within the operating voltage range (1.3 to 3.0
V). There is no impact on the duty function
7:5
SC
R/W
-
4
3
2
1
0
16Hz
8Hz
4Hz
2Hz
1Hz
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
Write 1 to set frequency to 16Hz
Write 1 to set frequency to 8Hz
Write 1 to set frequency to 4Hz
Write 1 to set frequency to 2Hz
Write 1 to set frequency to 1Hz
7.7Clock Adjustment Register Access (Command 110b)
Bit
Name
R/W Default
Description
7
V7
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
The clock adjustment register is a 1-byte register that is used to logically
correct real-time data. When not using the clock adjustment register, set
this register to 00h using the clock adjustment register write command.
6
5
4
3
2
V6
V5
V4
V3
V2
V0.12P
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FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
