Feature Integration Technology Inc.
Fintek
F15353
6 Functional Description
6.1 Power Supply Voltage Detector
Bit 7, POC flag, of status register_1 is set to 1 (“80h”) by the power-on detector and an 1Hz clock is output from
the INT1# pin. The oscillation frequency is adjustable. In the common condition, the F15353 must be initialized at
power-on. Initialization is performed by setting “1” to bit 0, RESET flag, of the status register_1. After the initialization,
the POC flag is set to “0”. In the common operation of the power-on detector, the supply voltage is held at 0Vand
then increasing it.
The state of every register after initialization is as following:
Table 1: Initialization States of Register
Real-time data register
Status register_1
00(year),01(month), 01(day), 0(day of week), 00(hour),
00(minute), 00(second)
“0 0 0 0 b3 b2 b1 0”b (The b3, b2, and b1 data of status
register_1 after initialization are set in b3, b2, b1)
Status register_2
INT1# register_1
INT1# register_2
Clock adjustment register
Free register
“00”h
“00”h
“00”h
“00”h
“00”h
6.2 Power Supply Voltage Detector
There is an internal power supply voltage detector, which monitors the power supply voltage drops by reading
the BLD flag, in the F15353. If the power supply voltage drops under the detect voltage (typical 1.2v), the BLD latch
circuit latches “H” level. Bit 6, BLD flag, of the internal status register_1 is set to “1”, and the sampling is stopped. If
the BLD flag is detected “1”, the detection is stopped until the initialization is performed or the flag is read by the
status register_1 access command, and “1” is held in the BLD flag. The resume condition of sampling operation is
the subsequent communication action initialized or the BLD flag read only. If the BLD flag is “1” after the power
supply voltage is recovered, it must be initialized additionally.
V0.12P
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FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
