FTRJ1721P1xCL Pluggable SFP Product Specification – December 2003
I.
Pin Descriptions
Pin
Symbol
Name/Description
Ref.
1
2
VEET
TFAULT
TDIS
Transmitter Ground (Common with Receiver Ground)
Transmitter Fault. Not supported.
1
3
Transmitter Disable. Laser output disabled on high or open.
2
3
3
3
4
5
1
1
1
4
MOD_DEF(2) Module Definition 2. Data line for Serial ID.
MOD_DEF(1) Module Definition 1. Clock line for Serial ID.
MOD_DEF(0) Module Definition 0. Grounded within the module.
Rate Select
LOS
5
6
7
No connection required
8
Loss of Signal indication. Logic 0 indicates normal operation.
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
9
VEER
VEER
VEER
RD-
10
11
12
13
14
15
16
17
18
19
20
RD+
VEER
VCCR
VCCT
VEET
TD+
TD-
1
1
1
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted DATA in. AC Coupled.
Transmitter Inverted DATA in. AC Coupled.
Transmitter Ground (Common with Receiver Ground)
VEET
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.
3. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and 3.6V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4. Finisar FTRJxx21xxxxx transceivers operate between OC-3 and OC-48, 1x and 2x Fibre Channel, and
Gigabit Ethernet data rates and respective protocols without active control. Finisar FTRJxx19xxxxx
transceivers operate at 1x and 2x Fibre Channel, and Gigabit Ethernet data rates and respective
protocols without active control.
5. LOS is open collector output. Should be pulled up with 4.7k – 10kohms on host board to a voltage
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
TD-
20
19
18
17
16
15
14
13
12
11
VeeT
1
2
TXFault
TD+
3
TX Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
VeeT
VccT
VccR
VeeR
RD+
RD-
4
5
Towards
Bezel
Towards
ASIC
6
7
8
9
VeeR
VeeR
VeeR
10
Diagram of Connector Block Pinout on the Host Board
Finisar Corporation December 17, 2003 Rev. G
Page 2
FINISAR [ FINISAR CORPORATION. ]
