FTLF1519P1xNL Pluggable SFP Product Specification – December 2005
I.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Descriptions
Symbol
V
EET
T
FAULT
T
DIS
MOD_DEF(2)
MOD_DEF(1)
MOD_DEF(0)
Rate Select
LOS
V
EER
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
Name/Description
Transmitter Ground (Common with Receiver Ground)
Transmitter Fault. Not supported.
Transmitter Disable. Laser output disabled on high or open.
Module Definition 2. Data line for Serial ID.
Module Definition 1. Clock line for Serial ID.
Module Definition 0. Grounded within the module.
No connection required
Loss of Signal indication. Logic 0 indicates normal operation.
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted DATA in. AC Coupled.
Transmitter Inverted DATA in. AC Coupled.
Transmitter Ground (Common with Receiver Ground)
Ref.
1
2
3
3
3
4
5
1
1
1
1
1
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on T
DIS
>2.0V or open, enabled on T
DIS
<0.8V.
3. Should be pulled up with 4.7k - 10 kohms on host board to a voltage between 2.0V and 3.6V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4. Finisar FTLFxx19xxxxx transceivers operate at 1x and 2x Fibre Channel, and Gigabit Ethernet data
rates and respective protocols without active control.
5. LOS is open collector output. Should be pulled up with 4.7k – 10 kohms on host board to a voltage
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
1
2
3
4
VeeT
TD-
TXFault
TD+
TX Disable
VeeT
MOD-DEF(2)
VccT
20
19
18
17
16
15
14
13
12
11
Towards
Bezel
5
6
7
8
9
10
MOD-DEF(1)
VccR
MOD-DEF(0)
VeeR
Rate Select
RD+
LOS
RD-
VeeR
VeeR
VeeR
Towards
ASIC
Pinout of Connector Block on Host Board
©
Finisar Corporation December 15, 2005 Rev A
Page 2