MC81F4x16
Figure 7-6 Waveform for UART Timing Characteristics
tSCK
Shift
Clock
tH1
tS1
D0
Data
Out
D1
D2
D3
D4
D5
D6
D7
tS2
Valid
tH2
Valid
Data
In
Valid
Valid
Valid
Valid
Valid
Valid
NOTE:
The symbols shown in this diagram are defined as follows:
fSCK
tS1
tS2
tH1
tH2
Serial port clock cycle time
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Figure 7-7 Timing Waveform for the UART Module
October 19, 2009 Ver.1.35
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