MC81F4x16
IDLE Mode
(Watchdog Timer Active)
Stop Mode
Normal
Operating Mode
Data Retention
VDDDR
VDD
Execution of
STOP Instruction
0.8VDD
INT Request
tWAIT
NOTE: tWAIT is the same as 256 X 1/BT Clock
Figure 7-4 Stop Mode Release Timing When Initiated by an Interrupt
RESET
Occurs
Oscillation
Stabillization Time
Stop Mode
Normal
Operating Mode
Data Retention
VDDDR
VDD
Execution of
STOP Instruction
RESETB
0.8VDD
0.2VDD
TWAIT
NOTE: tWAIT is the same as 256 X 1024 X 1/fxx (65.5mS @4MHz)
Figure 7-5 Stop Mode Release Timing When Initiated by RESETB
October 19, 2009 Ver.1.35
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