MC81F4x16
16.1 Registers
WDTR
WATCHDOG TIMER REGISTER
00F4H
7
6
5
4
3
2
1
0
WDTCL
WDTCMP
WDTR
Reset value: 7FH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0: Free-run count
1: When the WDTCL is set to “1”, binary
counter is cleared to “0”. And the WDTCL
becomes “0” automatically after one
machine cycle. Counter count up again.
WDTCL
Watchdog Timer Clear Bit
WDTCMP
bit6 – bit0
7-bit compare data
WDTSR
WATCHDOG TIMER STATUS REGISTER
00F6H
7
6
5
4
3
One byte register
R/W R/W
2
1
0
WDTSR
Reset value: 00H
R/W
R/W
R/W
R/W
R/W
R/W
10100101: Disable watchdog timer function
Others: Enable watchdog timer function
Watchdog Timer Function Disable Code
(for System Reset)
Figure 16-2 Watchdog Timer Timing
October 19, 2009 Ver.1.35
113
FINECHIPS [ FINECHIPS ]
