MC81F4x16
15.1 Registers
CKCTLR
CLOCK CONTROL REGISTER
00F2H
7
6
5
4
3
2
1
0
–
–
–
WDTON BTCL
R/W R/W
BTS
CKCTLR
Reset value: 17H
–
–
–
R/W
R/W
R/W
–
bit7 – bit5
Not used for MC81F4x16
0: Operate as 7-bit timer
1: Enable Watchdog timer
0: Normal operation (free-run)
WDTON
Watchdog Timer Enable Bit
1: Clear 8-bit counter (BITR) to “0”,
This bit becomes 0 automatically after one
machine cycle, and starts counting.
BTCL
Basic Timer Clear Bit
000: fxin/8
001: fxin/16
010: fxin/32
011: fxin/64
100: fxin/128
101: fxin/256
110: fxin/512
111: fxin/1024
Basic Interval Timer Source Clock
Selection Bits
BTS
Interrupt(overflow) period (ms)
@ fxin = 8MHz
CKCTLR[2:0]
Source clock
000
001
010
011
100
101
110
111
fxin/8
fxin/16
0.256
0.512
1.024
2.048
4.096
8.192
16.384
32.768
fxin/32
fxin/64
fxin/128
fxin/256
fxin/512
fxin/1024
Figure 15-1 Basic Interval Timer Interrupt Period
BTCR
BASIC TIMER COUNTER REGISTER
00F1H
7
6
5
4
3
2
1
0
BTCR
One byte register
Reset value: XXH
R
R
R
R
R
R
R
R
A 8 bit count register for the basic interval timer.
October 19, 2009 Ver.1.35
111
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