L
OW
N
OISE
, H
IGH
L
INEARITY
P
ACKAGED
PHEMTT
FPD1500SOT89
•
BIASING GUIDELINES
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD1500SOT89.
Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 2.6
Ω
for a 50% of I
DSS
operating point.
For standard Class A operation, a 50% of I
DSS
bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of I
DSS
. To achieve a larger separation between P
1dB
and IP3, an operating point in the 25%
to 33% of I
DSS
range is suggested. Such Class AB operation will not degrade the IP3
performance.
PACKAGE OUTLINE
(dimensions in mm)
•
PCB Foot Print
Units in inches
All information and specifications subject to change without notice.
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05
Email:
sales@filcsi.com
FILTRONIC [ FILTRONIC COMPOUND SEMICONDUCTORS ]
