Datasheet v3.0
1
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
SYMBOL
VDS
TEST CONDITIONS
ABSOLUTE MAXIMUM
7
-3V < VGS < -0.5V
12V
VGS
0V < VDS < +8V
For VDS > 2V
-3V
IDS
IDSS
IG
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
+20/-20mA
27.5dBm
175°C
2
RF Input Power
PIN
Channel Operating Temperature
Storage Temperature
TCH
TSTG
PTOT
-40°C to 150°C
6W
3
Total Power Dissipation
Notes:
1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device; Users should avoid exceeding 80% of 2 or more Limits simultaneously
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT
,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 6 - (0.04W/°C) x TPACK
where TPACK= source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 55°C carrier temperature: PTOT = 6W – (0.04 x (55 – 22)) = 4.68W
5For optimum heatsinking, metal-filled through (Source) via holes should be used directly below the central
metallized ground pad on the bottom of the package
6Thermal Resistivity: The nominal value of 25°C/W is measured with the package mounted on a large heatsink
with thermal compound to ensure adequate (unsoldered) contact. The package temperature is referred to the
Source leads.
7 Operating at absolute maximum VD continuously is not recommended. If operation is considered then IDS must
be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is restricted
to <-0.5V.
BIASING GUIDELINES:
•
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
•
•
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices such as the FPD1000AS.
The recommended 200mA bias point is nominally a Class AB mode. A small amount of RF gain
expansion prior to the onset of compression is normal for this operating point.
RECOMMENDED OPERATING BIAS CONDITIONS:
•
•
Drain-Source Voltage:
Quiescent Current:
From 5V to 10V
From 25% IDSS to 55% IDSS
2
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
FILTRONIC [ FILTRONIC COMPOUND SEMICONDUCTORS ]
