5V-Line
SPM
R
PF=4.7㏀
100Ω
100Ω
100Ω
,
,
IN(UH) IN(VH)
IN
(WH)
,
,
IN(UL) IN(VL)
IN(WL)
CPU
VFO
1nF
1nF
1nF
CPF= 1nF
COM
Note:
1) RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The
SPM input signal section integrates 5kΩ (typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input ter-
minal.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
Figure 11. Recommended CPU I/O Interface Circuit
These Values depend on PWM Control Algorithm
One-Leg Diagram of SPM
P
Vcc VB
IN
HO
15V-Line
0.1uF
22uF
COM VS
Inverter
Output
Vcc
IN OUT
1000uF
1uF
VSL
COM
N
Note:
1) The ceramic capacitor placed between V -COM should be over 1uF and mounted as close to the pins of the SPM as possible.
CC
Figure 12. Recommended Bootstrap Operation Circuit and Parameters
12
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FSBB30CH60C Rev. D
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
