FDS3672
PSPICE Electrical Model
.SUBCKT FDS3672 2 1 3 ;
Ca 12 8 6.0e-10
Cb 15 14 7.4e-10
Cin 6 8 2.0e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 107
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.61e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.98e-9
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 0.4e-2
Rgate 9 20 1.40
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 1.3e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),3))}
.MODEL DbodyMOD D (IS=5.0E-11 N=1.13 RS=4.4e-3 TRS1=2.0e-3 TRS2=1.0e-6
+ CJO=1.4e-9 M=0.58 TT=4.0e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.38 TRS1=2.0e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.9e-10 IS=1.0e-30 N=10 M=0.6)
.MODEL MstroMOD NMOS (VTO=4.05 KP=90 lambda=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.35 KP=6.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.40)
.MODEL MweakMOD NMOS (VTO=2.76 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.40e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.5e-4 TC2=-25.0e-7)
.MODEL RdrainMOD RES (TC1=1.5e-2 TC2=5.5e-5)
.MODEL RSLCMOD RES (TC1=1.0e-3 TC2=1.0e-6)
.MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-3.4e-3 TC2=-1.7e-5)
.MODEL RvtempMOD RES (TC1=-4.4e-3 TC2=2.2e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;
IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
RLGATE
CIN
rev October 2002
LDRAIN
DPLCAP
10
RSLC1
51
ESLC
50
RDRAIN
EVTHRES
+ 19 -
8
6
MSTRO
LSOURCE
8
RSOURCE
S1A
12
S1B
CA
13
+
EGS
-
6
8
EDS
-
13
8
S2A
14
13
S2B
CB
+
5
8
8
RVTHRES
14
IT
15
17
RBREAK
18
RVTEMP
19
-
VBAT
+
22
7
RLSOURCE
SOURCE
3
21
16
RLDRAIN
DBREAK
11
+
17
EBREAK 18
-
MWEAK
MMED
5
DRAIN
2
RSLC2
5
51
-
ESG
+
LGATE
EVTEMP
RGATE +
18 -
22
9
20
6
8
-
©2003 Fairchild Semiconductor Corporation
+
DBODY
FDS3672 Rev. B
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
