FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Electrical Characteristics
(Continued)
Symbol
Parameter
Lower Threshold
Upper Threshold
PG Output Low
Leakage Current
PG2/REF2OUT Voltage
DDR, EN Inputs
V
INH
V
INL
Input High
Input Low
FPWM Low
FPWM High
FPWM Connected to Output
0.9
2
0.8
0.1
V
V
V
V
Conditions
% of Set Point, 2µs Noise Filter
% of Set Point, 2µs Noise Filter
IPG = 4mA
V
PULLUP
= 5V
DDR = 1, 0mA < I
REF2OUT
≤10mA
Min.
-86
108
Typ. Max.
-94
116
0.5
1
Units
%
%
V
µA
%
V
REF2
Power-Good Output and Control Pins
99.00
1.01
FPWM Inputs
Block Diagram
5V
VDD
EN
BOOT
C
BOOT
VIN
Q1
FPWM/VOUT
SS
HYST
OVP
HYST
SW
Q2
V
DD
LDRV
PGND
Q
S
R
PWM
RAMP
PWM
PWM/HYST
R
SENSE
SH
/
L
OU T
POR/UVLO
FPWM
DDR
HDRV
V
O UT
C
OUT
DDR
VIN
ADAPTIVE
GATE
CONTROL LOGIC
OSC
CLK
RAMP
ILIM det.
MO
ISNS
VSEN
EA
DUTY
CYCLE
CLAMP
CURRENT PROCESSING
Σ
I
OU T
FPWM/VOUT
SS
V
REF
PGOOD
REF2
ILIM
R
ILIM
Reference and
Soft Start
PWM/HYST
DDR
Figure 4. IC Block Diagram
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
7
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
