FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Pin Descriptions
(Continued)
Pin #
13
Name
DDR
Description
DDR Mode Control.
HIGH = DDR Mode. LOW = two separate regulators operating 180° out
of phase.
Input Voltage.
Normally connected to battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
Power Good Flag.
An open-drain output that pulls LOW when V
SEN
is outside a ±10%
range of the 0.9V reference.
Power Good 2.
When not in DDR Mode, open-drain output that pulls LOW when the V
OUT
is
out of regulation or in a fault condition.
Reference Out 2.
When in DDR Mode, provides a buffered output of REF2. Typically used
as the V
DDQ/2
reference.
14
VIN
15
PG1
16
PG2 /
REF2OUT
18
Current Limit 2.
When not in DDR Mode, a resistor from this pin to GND sets the current
ILIM2 / REF2 limit.
Reference
for reg #2 when in DDR Mode. Typically set to V
OUT1 / 2
.
VCC
VCC.
This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
28
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
4
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