74LCX16245
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names
OE
n
T/R
n
A
0
–A
15
B
0
–B
15
NC
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
B
0
B
2
B
4
B
6
B
8
B
10
B
12
B
14
B
15
2
NC
B
1
B
3
B
5
B
7
B
9
B
11
B
13
NC
3
T/R
1
NC
V
CC
GND
GND
GND
V
CC
NC
T/R
2
4
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
5
NC
A
1
A
3
A
5
A
7
A
9
A
11
A
13
NC
6
A
0
A
2
A
4
A
6
A
8
A
10
A
12
A
14
A
15
Truth Tables
Inputs
Pin Assignment for FBGA
OE
1
L
L
H
Inputs
OE
2
L
L
H
T/R
2
L
H
X
Outputs
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH Z State on A
8
–A
15
, B
8
–B
15
T/R
1
L
H
X
Outputs
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH Z State on A
0
–A
7
, B
0
–B
7
(Top Thru View)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Logic Diagrams
Note:
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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