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6N136 参数 Datasheet PDF下载

6N136图片预览
型号: 6N136
PDF下载: 下载PDF文件 查看货源
内容描述: 高速晶体管光电耦合器 [HIGH SPEED TRANSISTOR OPTOCOUPLERS]
分类和应用: 晶体光电晶体管
文件页数/大小: 12 页 / 577 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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Single-channel: 6N135, 6N136 , HCPL-2503, HCPL-4502 Dual-Channel: HCPL-2530, HCPL-2531 High Speed Transistor Optocouplers
Isolation Characteristics
(T
A
= 0 to 70°C Unless otherwise specified)
Characteristics
Input-output
insulation leakage current
Test Conditions
(Relative humidity = 45%)
(T
A
= 25°C, t = 5 s)
(V
I-O
= 3000 VDC)
(Note 9)
(RH
50%, T
A
= 25°C)
(Note 9) ( t = 1 min.)
(Note 9) (V
I-O
= 500 VDC)
(Note 9) (f = 1 MHz)
(I
O
= 3 mA, V
O
= 5 V)
(RH
45%, V
I-I
= 500 VDC) (Note 10)
t = 5 s, (HCPL-2530/2531 only)
(V
I-I
= 500 VDC) (Note 10)
(HCPL-2530/2531 only)
(f = 1 MHz) (Note 10)
(HCPL-2530/2531 only)
Symbol
I
I-O
Min
Typ**
Max
1.0
Unit
µA
Withstand insulation test voltage
Resistance (input to output)
Capacitance (input to output)
DC Current gain
Input-Input
Insulation leakage current
Input-Input Resistance
Input-Input Capacitance
V
ISO
R
I-O
C
I-O
HFE
I
I-I
R
I-I
C
I-I
2500
10
12
0.6
150
0.005
10
11
0.03
V
RMS
pF
µA
pF
Notes
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C.
5. Current Transfer Ratio is defined as a ratio of output collector current, I
O
, to the forward LED input current, I
F
, times 100%.
6. The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1kΩ pull-up resistor.
7. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and 5.6 kΩ pull-up resistor.
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge of the com-
mon mode pulse signal V
CM
, to assure that the output will remain in a logic high state (i.e., V
O
>2.0 V). Common mode transient
immunity in logic low level is the maximum tolerable (negative) dV
cm
/dt on the trailing edge of the common mode pulse signal,
V
CM
, to assure that the output will remain in a logic low state (i.e., V
O
<0.8 V).
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
10. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
6
Single-channel: 6N135, 6N136 , HCPL-2503, HCPL-4502 Dual-Channel: HCPL-2530, HCPL-2531 Rev. 1.0.3
www.fairchildsemi.com