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100336QI 参数 Datasheet PDF下载

100336QI图片预览
型号: 100336QI
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗4级计数器/移位寄存器 [Low Power 4-Stage Counter/Shift Register]
分类和应用: 移位寄存器计数器触发器逻辑集成电路
文件页数/大小: 14 页 / 152 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
 浏览型号100336QI的Datasheet PDF文件第2页浏览型号100336QI的Datasheet PDF文件第3页浏览型号100336QI的Datasheet PDF文件第4页浏览型号100336QI的Datasheet PDF文件第5页浏览型号100336QI的Datasheet PDF文件第7页浏览型号100336QI的Datasheet PDF文件第8页浏览型号100336QI的Datasheet PDF文件第9页浏览型号100336QI的Datasheet PDF文件第10页  
SOIC and PLCC AC Electrical Characteristics  
V
EE = −4.2V to 5.7V, VCC = VCCA = GND  
T
C = 0°C  
Max  
T
C = +25°C  
TC = +85°C  
Symbol  
Parameter  
Units  
MHz  
ns  
Conditions  
Figures 2, 3  
Min  
Min  
Max  
Min  
Max  
fSHIFT  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPHL  
Shift Frequency  
350  
350  
350  
Propagation Delay  
CP to Qn, Qn  
Figures 1, 2  
(Note 6)  
1.00  
2.10  
2.40  
1.40  
2.80  
2.40  
1.80  
1.90  
0.35  
1.80  
3.30  
4.20  
2.30  
4.90  
3.80  
2.90  
3.90  
1.10  
1.00  
2.10  
2.40  
1.40  
2.90  
2.40  
1.80  
1.90  
0.35  
1.80  
3.30  
4.20  
2.30  
5.00  
3.80  
2.90  
3.90  
1.10  
1.00  
2.10  
2.60  
1.50  
3.10  
2.50  
1.90  
2.10  
0.35  
1.80  
3.50  
4.50  
2.40  
5.30  
3.90  
3.10  
4.20  
1.10  
Propagation Delay  
CP to TC (Shift)  
Propagation Delay  
CP to TC (Count)  
Propagation Delay  
MR to Qn, Qn  
Figures 1, 7, 8  
(Note 6)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Figures 1, 9  
(Note 6)  
Figures 1, 4  
(Note 6)  
Propagation Delay  
MR to TC (Count)  
Propagation Delay  
MR to TC (Shift)  
Propagation Delay  
D0/CET to TC  
Figures 1, 12  
(Note 6)  
Figures 1, 10, 11  
(Note 6)  
tPLH  
tPHL  
tPLH  
tPHL  
tTLH  
tTHL  
tS  
Figures 1, 5  
(Note 6)  
Propagation Delay  
Sn to TC  
Transition Time  
20% to 80%, 80% to 20%  
Setup Time  
Figures 1, 3  
D3  
0.90  
1.40  
1.20  
1.30  
3.30  
2.50  
0.90  
1.40  
1.20  
1.30  
3.30  
2.50  
0.90  
1.40  
1.20  
1.30  
3.30  
2.50  
Pn  
D0/CET  
ns  
Figures 4, 6  
CEP  
Sn  
MR (Release Time)  
Hold Time  
tH  
D3  
0.30  
0.20  
0.20  
0.10  
0.00  
0.30  
0.20  
0.20  
0.10  
0.00  
0.30  
0.20  
0.20  
0.10  
0.00  
Pn  
Figure 6  
D0/CET  
ns  
CEP  
Sn  
tPW(H)  
Pulse Width HIGH  
CP, MR  
2.00  
2.00  
2.00  
ns  
ps  
Figures 3, 4  
tOSHL  
Maximum Skew Common Edge  
Output-to-Output Variation  
Clock to Output Path  
Maximum Skew Common Edge  
Output-to-Output Variation  
Clock to Output Path  
Maximum Skew Opposite Edge  
Output-to-Output Variation  
Clock to Output Path  
Maximum Skew  
Pin (Signal) Transition Variation  
Clock to Output Path  
PLCC Only  
(Note 7)  
200  
200  
230  
245  
200  
200  
230  
245  
200  
200  
230  
245  
tOSLH  
tOST  
tPS  
PLCC Only  
(Note 7)  
ps  
ps  
ps  
PLCC Only  
(Note 7)  
PLCC Only  
(Note 7)  
Note 6: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.  
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-  
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite  
directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design  
www.fairchildsemi.com  
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