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100331SCX 参数 Datasheet PDF下载

100331SCX图片预览
型号: 100331SCX
PDF下载: 下载PDF文件 查看货源
内容描述: 三重D型触发器\n [Triple D-Type Flip-Flop ]
分类和应用: 触发器锁存器逻辑集成电路光电二极管输入元件
文件页数/大小: 10 页 / 103 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
 浏览型号100331SCX的Datasheet PDF文件第2页浏览型号100331SCX的Datasheet PDF文件第3页浏览型号100331SCX的Datasheet PDF文件第4页浏览型号100331SCX的Datasheet PDF文件第5页浏览型号100331SCX的Datasheet PDF文件第7页浏览型号100331SCX的Datasheet PDF文件第8页浏览型号100331SCX的Datasheet PDF文件第9页浏览型号100331SCX的Datasheet PDF文件第10页  
Industrial Version  
PLCC DC Electrical Characteristics (Note 5)  
V
EE = −4.2V to 5.7V, VCC = VCCA = GND, TC = −40°C to +85°C  
T
C = −40°C  
TC = 0°C to +85°C  
Symbol  
Parameter  
Units  
Conditions  
Min  
Max  
870  
Min  
Max  
870  
VOH  
VOL  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
1085  
1830  
1095  
1025  
1830  
1035  
mV  
mV  
mV  
mV  
mV  
V
IN = VIH (Max)  
or VIL (Min)  
IN = VIH (Min)  
or VIL (Max)  
Loading with  
50to 2.0V  
Loading with  
50to 2.0V  
1575  
1620  
VOHC  
VOLC  
VIH  
V
1565  
870  
1610  
870  
1170  
1830  
0.5  
1165  
1830  
0.5  
Guaranteed HIGH Signal  
for All Inputs  
VIL  
Input LOW Voltage  
1480  
1475  
mV  
Guaranteed LOW Signal  
for All Inputs  
IIL  
Input LOW Current  
Input HIGH Current  
Power Supply Current  
µA  
µA  
V
IN = VIL (Min)  
IN = VIH (Max)  
IIH  
IEE  
300  
240  
V
122  
60  
122  
65  
mA  
Inputs Open  
Note 5: The specified limits represent the worst casevalue for the parameter. Since these values normally occur at the temperature extremes, additional  
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-  
sen to guarantee operation under worst caseconditions.  
PLCC AC Electrical Characteristics  
V
EE = −4.2V to 5.7V, VCC = VCCA = GND  
T
C = −40°C  
T
C = +25°C  
TC = +85°C  
Symbol  
Parameter  
Units  
Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
fMAX  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tTLH  
tTHL  
tS  
Toggle Frequency  
Propagation Delay  
CPC to Output  
375  
400  
400  
MHz Figures 2, 3  
0.75  
1.80  
1.80  
1.50  
1.80  
2.40  
2.60  
1.40  
0.75  
0.75  
0.70  
0.70  
1.10  
1.10  
0.35  
1.80  
1.80  
1.50  
1.80  
2.40  
2.60  
1.10  
0.75  
0.75  
0.70  
0.70  
1.10  
1.10  
0.35  
1.80  
1.80  
1.60  
1.80  
2.40  
ns  
Figures 1, 3  
Propagation Delay  
CPn to Output  
0.70  
0.60  
0.70  
1.10  
1.10  
0.20  
ns  
Propagation Delay  
CDn, SDn to Output  
CPn, CPC = L  
CPn, CPC = H  
CPn, CPC = L  
CPn, CPC = H  
Figures 1, 3, 4  
Figure 5  
ns  
Figures 1, 4  
Propagation Delay  
MS, MR to Output  
ns  
ns  
2.60  
1.10  
Transition Time  
20% to 80%, 80% to 20%  
Setup Time  
Dn  
1.00  
1.50  
2.50  
0.7  
0.30  
1.20  
2.20  
0.5  
0.30  
1.20  
2.20  
0.7  
CDn, SDn (Release Time)  
MS, MR (Release Time)  
Hold Time Dn  
ns  
ns  
ns  
Figure 4  
Figure 5  
tH  
tPW(H)  
Pulse Width HIGH  
CPn, CPC, CDn,  
SDn, MR, MS  
2.00  
2.00  
2.00  
Figures 3, 4  
www.fairchildsemi.com  
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