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100310 参数 Datasheet PDF下载

100310图片预览
型号: 100310
PDF下载: 下载PDF文件 查看货源
内容描述: 低偏移2 : 8差分时钟驱动器 [Low Skew 2:8 Differential Clock Driver]
分类和应用: 时钟驱动器
文件页数/大小: 6 页 / 66 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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100310
Industrial Version
DC Electrical Characteristics
(Note 8)
V
EE
= −4.2V
to
−5.7V,
V
CC
=
V
CCA
=
GND
Symbol
V
OH
V
OL
V
OHC
V
OLC
V
BB
V
DIFF
V
CM
V
IH
V
IL
I
IL
I
IH
I
CBO
I
EE
Parameter
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Reference Voltage
Input Voltage Differential
Common Mode Voltage
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
Input HIGH Current
Input Leakage Current
Power Supply Current
−10
−100
−40
−1395
150
−1170
−1830
0.50
240
−10
−100
−40
−870
−1480
T
C
= −40°C
Min
−1085
−1830
−1095
−1565
−1255
−1380
150
−1165
−1830
0.50
240
−870
−1475
Max
−870
−1575
T
C
=
0°C to
+85°C
Min
−1025
−1830
−1035
−1610
−1260
Max
−870
−1620
Units
mV
mV
mV
mV
mV
mV
V
mV
mV
µA
µA
µA
mA
Guaranteed HIGH Signal for
All Inputs
Guaranteed LOW Signal for
All Inputs
V
IN
=
V
IL
(Min)
V
IN
=
V
IH
(Max)
V
IN
=
V
EE
Inputs Open
Conditions
V
IN
=
V
IH
(Max)
or V
IL
(Min)
V
IN
=
V
IH
or V
IL
(Min)
I
VBB
= −250 µA
Required for Full Output Swing
Loading with
50Ω to
−2.0V
Loading with
50Ω to
−2.0V
V
CC
2.0 V
CC
0.5 V
CC
2.0 V
CC
0.5
Note 8:
The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
AC Electrical Characteristics
V
EE
= −
4.2V to
5.7V, V
CC
=
V
CCA
=
GND
Symbol
f
MAX
Parameter
Max Toggle Frequency
CLKIN A/B to Q
n
SEL to Q
n
t
PLH
t
PHL
Propagation Delay,
CLKIN
n
, to CLK
n
Differential
Single-Ended
t
PLH
t
PHL
t
PS
t
OSLH
t
OSHL
t
OST
t
S
t
H
t
TLH
t
THL
Propagation Delay
SEL to Output
LH-HL Skew
Gate-Gate Skew LH
Gate-Gate Skew HL
Gate-Gate LH-HL Skew
Setup Time
SEL to CLKIN
n
Setup Time
SEL to CLKIN
n
Transition Time
20% to 80%, 80% to 20%
300
0
275
510
750
0.78
0.78
0.70
0.88
0.95
0.99
10
20
20
30
0.98
1.18
1.20
30
50
50
60
300
0
275
500
750
0.82
0.82
0.80
0.92
0.98
1.02
10
20
20
30
1.02
1.22
1.25
30
50
50
60
300
0
275
480
750
0.89
0.89
0.85
1.01
1.06
1.10
10
20
20
30
1.09
1.29
1.35
30
50
50
60
ps
ps
ps
Figure 4
ps
ns
Figure 2
(Note 9)(Note 12)
(Note 10)(Note 12)
(Note 10)(Note 12)
(Note 11)(Note 12)
ns
Figure 3
750
575
750
575
750
575
MHz
MHz
T
C
= −40°C
Min
Typ
Max
Min
T
C
= +25°C
Typ
Max
Min
T
C
= +85°C
Typ
Max
Units
Conditions
Note 9:
t
PS
describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW prop-
agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin.
Note 10:
t
OSLH
describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; t
OSHL
describes the same
conditions except with the outputs going HIGH-to-LOW.
Note 11:
t
OST
describes the maximum worst case difference in any of the t
PS
, t
OSLH
or t
OST
delay paths combined.
Note 12:
The skew specifications pertain to differential I/O paths.
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