E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
CS#
0
1
2
3
4
5
6
7
SCK
Instruction
SI
1
1
0
1
0
1
0
1
Figure 22. Erase Parameter Page( PE ) Instruction Sequence
1) Vcc (min) at power-up, and then for a further
Erase Parameter Page(PE)
delay of t (as described in Table 5)
PU
2) Vss at power-down
The Erase Parameter Page Instruction sets all 256
bytes of memory in the Parameter Page to the
erased state of all 1s (FFh). A Write Enable instruc-
tion must be executed before the device will accept
the Erase Parameter Page instruction(Status Regis-
ter bit WEL must equal 1). The instruction is initiated
by driving the CS# pin low and shifting the instruc-
tion code “D5h”. The Erase Parameter Page instruc-
tion sequence is shown in Figure 22.
A simple pull-up resistor on Chip Select (CS#) can
usually be used to insure safe and proper power-up
and power-down.
The device ignores all instructions until a time delay
of t (as described in Table 5) has elapsed after the
PU
moment that Vcc rises above the minimum Vcc
threshold. However, correct operation of the device
is not guaranteed if by this time Vcc is still below Vcc
(min). No Write Status Register, Program or Erase
The CS# pin must be driven high after the eighth has
been latched. If this is not done the Erase Parameter
Page instruction will not be executed. After CS# is
driven high, the self-timed Erase Parameter Page
instructions should be sent until t
after Vcc
PU
reaches the minimum Vcc threshold (See Figure
23).
instuction will commence for a time duration of t
.
PE
While the Erase Parameter Page Cycle is in
progress, the Read Status Register instruction may
still be accessed to check the status of the WIP bit.
The WIP bit is a 1 during the Erase Parameter Page
cycel and becomes a 0 when finished and the device
is ready to accept other instructions again. After the
Erase Parameter Page cycle has started the Write
Enable Latch(WEL) bit in the Status Register is
cleared to 0. The Erase Parameter Page instruction
will not be executed if any page is protected by the
Block Protect(BP2, BP1, BP0) bits.
At power-up, the device is in Standby mode (not
Deep Power Down mode) and the WEL bit is reset.
Normal precautions must be taken for supply rail
decoupling to stabilize the Vcc feed. Each device in
a system should have the Vcc rail decoupled by a
suitable capacitor close to the package pins (this
capacitor is generally of the order of 0.1uF).
At power-down, when Vcc drops from the operating
voltage to below the minimum Vcc threshold, all
operations are disabled and the device does not
respond to any instructions. (The designer needs to
be aware that if a power-down occurs while a Write,
Program or Erase cycle is in progress, data corrup-
tion can result.)
Power-up and Power-down
The device must not be selected at power-up or
power-down (that is, CS# must follow the voltage
applied on Vcc) until Vcc reaches the correct value
as follows:
26
Rev. 0E May 11 , 2006
ES25P16
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
