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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
REV. 1.0.1  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
4.13 High-Speed Multiplexed Interface  
In addition to the non-multiplexed mode, the framer can interface through the backplane in a high-speed  
multiplexed application, either through a bit-muxed or byte-muxed (in HMVIP or H.100) manner. In this mode,  
the chip is divided into two multiplexed blocks, four channels per block. For T1, the high speed multiplexed  
modes are 12.352Mbps (bit-muxed, TxSYNC is “High” during the F-bit), 16.384Mbps (bit-muxed, TxSYNC is  
“High” during the F-bit), 16.384Mbps (HMVIP: byte-muxed, TxSYNC is “High” during the last 2-bits of the  
previous frame and the first 2-bits of the current frame), or 16.384Mbps (H.100: byte-muxed, TxSYNC is “High”  
during the last bit of the previous frame and the first bit in the current frame). For E1 mode, the only mode that  
is not supported is the 12.352Mbps. The only other difference is that the F-bit (for T1 mode) becomes the first  
bit of the E1 frame. Figure 25 is a simplified block diagram of transmit bit-muxed application. Figure 26 is a  
simplified block diagram of receive bit-muxed application. Although the data is only applied to channel 4 or  
channel 0, the TxSERCLK is necessary for all channels so that the transmit line rate is always equal to the T1/  
E1 carrier rate.  
F
IGURE 25. TRANSMIT HIGH-SPEED BIT MULTIPLEXED BLOCK DIAGRAM  
TxSYNC0  
Bit Interleaved Multiplexed Mode  
0b2 0b1  
1b2 1b1  
2b2 2b1  
3b2 3b1  
TTIP/TRing0  
TTIP/TRing1  
TTIP/TRing2  
TTIP/TRing3  
0b0  
1b0  
TxMSYNC0  
(16.384MHz)  
DMUX  
3b2 3b2 2b2 2b2 1b2 1b2 0b2 0b2  
TxSER0  
3b1 3b1 2b1 2b1 1b1 1b1 0b1 0b1 3b0 3b0 2b0 2b0 1b0 1b0 0b0 0b0  
2b0  
3b0  
TxSERCLK0  
(2.048MHz)  
TxSERCLK1  
(2.048MHz)  
TxSERCLK2  
(2.048MHz)  
TxSERCLK3  
(2.048MHz)  
F
IGURE 26. RECEIVE  
HIGH-SPEED  
B
IT  
M
ULTIPLEXED  
B
LOCK  
D
IAGRAM  
RxSYNC0  
Bit Interleaved Multiplexed Mode  
0b0 0b1 0b2  
1b0 1b1 1b2  
2b0 2b1 2b2  
3b0 3b1 3b2  
RTIP/RRing0  
RTIP/RRing1  
RTIP/RRing2  
RTIP/RRing3  
RxSERCLK0  
(16.384MHz)  
MUX  
0b2  
0b1 0 1b1 0  
2b1 0 3b1 0  
0
1b2  
0
2b2 0 3b2 0  
RxSER0  
0b0  
0 3b0  
1b0 0 2b0 0 0  
RZ Data  
RxLineClk0  
(2.048MHz)  
RxLineClk1  
(2.048MHz)  
RxLineClk2  
(2.048MHz)  
RxLineClk3  
(2.048MHz)  
156  
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