XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 119: FRAMER
I
NTERRUPT
E
NABLE
REGISTER T1 MODE
R
EGISTER 533 T1 MODE
IT UNCTION
F
RAMER
I
NTERRUPT
E
NABLE
R
EGISTER (FIER)
HEX ADDRESS: 0X0B05
B
F
T
YPE
D
EFAULT
DESCRIPTION-OPERATION
5
SIG_ENB
R/W
0
This bits enables the generation of an interrupt when any signaling
channel has changed state.
0 = Change of signaling data does not generate an interrupt.
1 = Change of signaling data does generate an interrupt.
4
3
COFA_ENB
R/W
R/W
0
0
Setting this bit will enable the interrupt generation when the frame
search logic determines that frame alignment has been reached and
that the new alignment differs from the previous alignment.
0 = Disables the interrupt generation of COFA detection.
1 = Enables the interrupt generation of COFA detection.
IF_ENB
IF Enable
Setting this bit will enable the interrupt generation of an in-frame rec-
ognition.
0 = Disables the interrupt generation of an in-frame detection.
1 = Enables the interrupt generation of an in-frame detection.
2
1
FMD_ENB
SE_ENB
R/W
R/W
0
0
FMD Enable
Setting this bit will enable the interrupt generation when the frame
search logic detects the presence of framing bit mimics.
0 = Disables the interrupt generation of framing mimic detection.
1 = Enables the interrupt generation of framing mimic detection.
Sync (CRC-4) Error Interrupt Enable
Setting this bit will enable the generation of an interrupt when a syn-
chronization bit error event has been detected. A synchronization
bit error event is defined as CRC-4 error.
0 = The detection of synchronization bit errors does not generate an
interrupt.
1 = The detection of synchronization bit errors does generate an
interrupt
0
FE_ENB
R/W0
0
Framing Bit Error Interrupt Enable
This bits enables the generation of an interrupt when a framing bit
error has been detected.
0 = Any error in the framing bits does not generate an interrupt.
1 = A error in the framing bits does generate an interrupt.
103
EXAR [ EXAR CORPORATION ]
