xr
XR17D154
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
FIGURE 21. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD
CLK
Host
1
7
2
3
4
5
6
8
9
10
11
FRAME#
Host
Data
BYTE
Data
WORD
AD[31:0]
Address
Host
Target
Bus
CMD
C/BE[3:0]#
Host
Byte Enable# = DWORD
Byte Enable# = BYTE
IRDY#
Host
TRDY#
Target
DEVSEL#
Target
Data
Parity
Data
Parity
Address
Parity
PAR
Host
Target
Active
Active
PERR#
Target
STEaRrgRe #
Active
t
Note: PERR# and SERR are optional in a bus target application.
Even Parity is on AD[31:0], C/BE[3:0]#, and PAR
PCI_RD1
59