欢迎访问ic37.com |
会员登录 免费注册
发布采购

SP708EN 参数 Datasheet PDF下载

SP708EN图片预览
型号: SP708EN
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗微处理器监控电路 [Low Power Microprocessor Supervisory Circuits]
分类和应用: 微处理器光电二极管监控输入元件
文件页数/大小: 18 页 / 1041 K
品牌: EXAR [ EXAR CORPORATION ]
 浏览型号SP708EN的Datasheet PDF文件第1页浏览型号SP708EN的Datasheet PDF文件第2页浏览型号SP708EN的Datasheet PDF文件第3页浏览型号SP708EN的Datasheet PDF文件第5页浏览型号SP708EN的Datasheet PDF文件第6页浏览型号SP708EN的Datasheet PDF文件第7页浏览型号SP708EN的Datasheet PDF文件第8页浏览型号SP708EN的Datasheet PDF文件第9页  
PIN DESCRIPTION  
SP705/706  
SP707/708  
SP813L  
NAME  
FUNCTION  
DIP/  
DIP/  
SOIC  
DIP/  
SOIC  
µSOIC  
SOIC  
µSOIC  
µSOIC  
Manual Reset - This input triggers a reset pulse  
when pulled below 0.8V. This active-LOW input  
has an internal 250µA pull-up current. It can be  
driven from a TTL or CMOS logic line or shorted  
to ground with a switch  
MR  
1
3
1
3
1
3
VCC  
+5V power supply  
2
3
4
5
2
3
4
5
2
3
4
5
GND  
Ground reference for all signals  
Power-Fail Input - When this voltage monitor input  
is less than 1.25V, PFO goes LOW. Connect PFI  
to ground or VCC when not in use.  
PFI  
4
5
6
7
4
5
6
7
4
5
6
7
Power-Fail Output - This output is HIGH until PFI  
is less than 1.25V.  
PFO  
Watchdog Input - If this input remains HIGH or  
LOW for 1.6s, the internal watchdog timer times  
out and WDO goes LOW. Floating WDI or  
connecting WDI to a high-impedance tri-state  
buffer disables the watchdog feature. The internal  
watchdog timer clears whenever RESET is  
asserted, WDI is tri-stated, or whenever WDI sees  
a rising or falling edge.  
WDI  
N.C.  
6
-
8
-
-
-
6
-
8
-
No Connect.  
6
7
8
1
Active-LOW RESET Output - This output pulses  
LOW for 200ms when triggered and stays LOW  
whenever VCC is below the reset threshold (4.65V  
for the SP705/707/813L and 4.40V for the  
SP706/708). It remains LOW for 200ms after Vcc  
rises above the reset threshold or MR goes from  
LOW to HIGH. A watchdog timeout will not trigger  
RESET unless WDO is connected to MR.  
RESET  
7
1
-
-
Watchdog Output - This output pulls LOW when  
the internal watchdog timer finishes its 1.6s count  
and does not go HIGH again until the watchdog is  
cleared. WDO also goes LOW during low-line  
conditions. Whenever VCC is below the reset  
threshold, WDO stays LOW. However, unlike  
RESET, WDO does not have a minimum pulse  
width. As soon as VCC is above the reset  
WDO  
8
2
-
-
8
7
2
1
threshold, WDO goes HIGH with no delay.  
Active-HIGH RESET Output - This output is the  
complement of RESET. Whenever RESET is  
HIGH, RESET is LOW, and vice versa. Note the  
SP813L/813M has a reset output only.  
RESET  
-
-
8
2
Table 1. Device Pin Description  
June 2008 Rev C  
SP705 Low Power Microprocessor Supervisory Circuits  
© 2008 Exar Corporation  
4
 复制成功!