MP8831
1
CNTL-A
CNTL-B
0
1
t
13
0
Pass-through Input Data
t
11
t
14
AD[7:0]
(Input)
ADC Output Data
Data A
Data B
Data C
ADC Output Data
t
10
t
12
t
12
t
12
t
15
DA[7:0]
(Output)
DAC Data Input
Data A
Data B
Data C
Pass-Through output data
Figure 4. Pass-Through Mode (AD=>DA) Timing Diagram
1
CNTL-A
0
1
CNTL-B
0
Pass-Through Output Data
t
16
t
18
AD[7:0]
(Output)
ADC Data Output
Data A
Data B
Data C
ADC Data Output
t
17
t
17
DA[7:0]
(Input)
Data A
Pass-through Input Data
Data B
Data C
Figure 5. Pass-Through mode (DA=>AD) Timing Diagram
Pass-Through Mode
OPERATION MODES
AD => DA (CNTL-A=low, CNTL-B=high)
DA => AD (CNTL-A=high, CNTL-B=low)
The two signals CNTL-A & CNTL-B are used to put the
chip into one of the four operation modes.
The pass-through modes are intended to allow the digital
ASIC (or µprocessor, DSP, etc) to read from and write to
the memory bank which holds the gain and offset DAC
data, without requiring a separate data bus between the
ASIC and the memory. In the AD => DA mode, pins
AD[7:0] are programmed as digital inputs, and they
simply pass data (through an internal bus) to pins DA[7:0]
whichareprogrammedasdigitaloutputs. IntheDA=>AD
mode things are reversed, DA[7:0] are programmed as
Convert Mode (CNTL-A=high, CNTL-B=high)
This is the normal operation mode. Data for the offset &
gain DACs is read in from the DA bus, and ADC data is
output on the AD bus.
Rev. 1.00
9
EXAR [ EXAR CORPORATION ]
