MP8831
digital inputs and AD[7:0] are programmed as digital
outputs. Please note that when DA[7:0] are used as
inputs they accept TTL level signals, when AD[7:0] are
used as inputs they accept CMOS level inputs.
DOFFSET
64
+ ǒ0.178 )
@ 0.170Ǔ
VRB
@ VREF
DGAIN
While in either of the pass-through modes, CLK-A &
CLK-B should both be held high.
+ ǒ Ǔ
VRT – VRB
@ 2.82 @ VREF
1024
Test Mode (CNTL-A=low, CNTL-B=low)
DGAIN
1024
ǒ Ǔ
VRT
+
NJ
@ 2.82 @ VREF
Nj
) VRB
This mode is used to test the gain and offset DACs. The
ADC reference voltages are output on the two MSB pins
of the AD bus, V on pin AD9 and V on pin AD8. The
RT
RB
Note:
data from the DA bus is read in to the DACs the same as
during normal conversion operation (i.e. on the rising
edges of CLK-A & CLK-B).
The output of the Gain DAC becomes non-linear when VRT
calculated using the above equations, is higher than
,
VDD-1.6V. The ADC itself remains linear, but its input range,
set by the DACs, deviates from the calculated values. This
can only happen if VREF is larger than 1.068V.
Controlling ADC Gain and Offset
The input range of the ADC is set by the voltages at its top
(V )andbottom(V )referencenodes. TheOffsetDAC
RT
RB
sets the voltage at the V node. The Gain DAC sets the
RB
span V -V . The following equations relate the DAC
RT RB
codes to the voltages at V & V :
RB
RT
V
REF
= voltage at V , pin 18
REF
D
D
= Offset DAC code, 6 bits, OS[5:0]
OFFSET
= Gain DAC code, 10 bits, GD[9:0]
GAIN
10
Sensor
Difference
(CCD)
V
IN
AD[9:0]
Clocks
CLK A
CLK B
MP8831
Reference
Input
REF
Controls
Cntl A
Cntl B
DA[7:0]
Computer
Interface
Micro Processor
or
Digital ASIC
8
R/W
RAM for
Gain & Offset
Data
Address
Figure 6. General Scanner System Using the MP8831
Rev. 1.00
10
EXAR [ EXAR CORPORATION ]
