MP8830
VREF range for each channel can be either the same or different
depending on the application and nominal channel gain re-
quired. A higher VREF provides lower channel gain.
ADC Gain and Offset Control
Each channel of the MP8830 contains a 10-bit ADC, a 10-bit
DAC with MSB = 1 (9 active bits) driving the positive reference,
and a 6-bit DAC driving the negative reference of the ADCs lad-
der network.
AV
DD
VINMX
250Ω
Sample
100Ω
The relationship between the ADC gain and offset and the
DAC data can be expressed mathematically.
25 pF 100Ω
A
IN
8 pF
Assign the terms VRT and VRB to represent the voltages for
the ADC full scale and black levels. DgainA and DoffsetA repre-
sent the digital value for the gain and offset parameters set by
the DACs for channel A.
V
SS
Sample
Sample
AV
1.5 pF
DD
+
–
VINMX
10 pF
VRT and VRB are defined by the equation:
VRT + VRB
2
V
CAL
DgainA
+ NJ(1 )
) < 1.3Nj
VRT
< VREF ) VRB
V
SS
29
DoffsetA
+ NJ(1 )
) < 0.16Nj
VRB
< VREF
Figure 8. ADC Input Equivalent Circuit
26
DgainA
+ NJ(1 )
) < 1.3Nj
VRT * VRB
< VREF
29
ADC Analog Input
This part has a switched capacitor type input circuit. This
means that the input impedance changes with the phase of the
input clock. Figure 8. shows an equivalent input circuit.
AV
DD
V
REF
AFORC
LM324A
ASENS
+
–
VCAL and VINMX
Channel
A
↓ IREF
VCAL voltage is connected through an analog mux to all 3
channel inputs at VINMX=1. VCAL can then be used to normal-
izeallthreeADCinputvoltagetooutputstates. Itcanbeusedfor
testing as well as building calibration tables for all three chan-
nels.
Circuitry
↓ 6.75 IREF
500Ω
Internal
V
Common
Internal Pad
~0.7Ω
AGND2 Pin
Supply and Grounds
Bonding
Wire & pin
AGND1, BGND1, CGND1, and GND3 should be connected
under the package to make their common impedance as low as
possible. AGND2, BGND2, CGND2 should also be connected
to this ground.
Figure 7. Driving the AFORC and ASENS Pins
(Channel A Example)
Use a single supply to drive all of the VDD pins. AVDD, BVDD
,
CVDD, VDD3 should be connected to a common supply plane
which forms a supply / ground plane with the analog ground
plane. In addition, local decoupling (preferably 0.1 uFchip type)
should be connected between each analog VDD pin and its clos-
est analog ground.
Channel Bias Circuitry
The gain DAC and the offset DAC for each channel have a
combinedbias generator for setting their full scale range. An ex-
ternal op amp is required and is connected per Figure 7. The
A decoupling capacitor (preferably 0.1 uFchip type) should
be connected across pin 1 and 64 and between pin 44 and 43. A
DVDD to DGND supply/ground plane should also be provided.
Rev. 1.00
12
EXAR [ EXAR CORPORATION ]
