MP8830
000(hex) to 001(hex) transition. This 4 LSB offset allows the
ADC to measure as low as –4 LSB of the analog input voltage
relative to the clamp voltage. To increase the negative input de-
tectable range, clamp with the offset DAC at a code higher than
00(hex).
Gain
DAC
9
Logic
6
C
DC
ACLP
AAN
The second terminal of the clamp switch is connected to a pin
with its corresponding channel prefix. For channel A, the pin is
named ACLP.
ADC
A
IN
DT/H
CMP
+
–
10
The control of the all the switches is provided by a separate
unlatched logic input called DCL. The delay from DCL falling
edge to switch on is specified as t16. The actual time required to
store the bias voltage depends on the external C value, and bias
variation from sample to sample. The equivalent impedance of
the clamp is 100Ω typical, spec name of RON, and must be in-
cluded in the analysis of the zero sample time considerations.
Offset
DAC
Channel A of MP8830
Figure 5. Simplified Diagram
Channel A Example
The black level is a function of the offset DAC, and therefore
requires that the value of the offset DAC be loaded into the offset
DAC second register before the clamp is turned on. This value
can be set from 00(hex) to 3F(hex) corresponding to a clamp
level change of ZSR.
Black Level Switch Operation
The MP8830 is equipped with a black level setting switch.
The function of the black level setting switch is to store the DC
offset value of the ADC as well as the common mode value of
AIN across the external CDC-hold capacitor. This is a cost effec-
tive method to store the black level of AIN or the offset of the sys-
tem. Note that the ACLP, BCLP, and CCLP level is DC shifted to
accommodate for the distribution of ADC offset.
The voltage swing at the ACLP, BCLP, CCLP pin after clamp
should be limited to the range of AVDD to AGND. This will pre-
vent the stored charge on the holding cap from being changed
by the input protection devices.
A 50Ω to 100Ω resistor in series with the ACLP, BCLP, CCLP
pin will limit the current induced in the protection and parasitic
diodes due to over-voltages induced by the source. Limit this
current with the use of external protection diodes.
One terminal of each clamp switch is connected at the ladder
tap voltage which corresponds to +4 LSB from the ADC
MSB=1
9
m
m
m
First
Gain
Register
R
R
2nd
Register
DAC
Decoder
9
–
V
RT
Gain DAC
Control
Data
+
V
Gain
REF
R
R
R
LAD
To
10-Bit
ADC
10
6
n
n
n
n
First
Offset
Register
R
R
R
2nd
Register
Decoder
DAC
V
RB
–
Offset
DAC
Control
Data
+
V
Offset
REF
R
Figure 6. MP8830 Single-Channel Equivalent Circuit
Rev. 1.00
11
EXAR [ EXAR CORPORATION ]
