MP8799
Figure 7. gives a visual definition of the INL error. The chart
shows a 3-bit converter transfer curve with greatly exaggerated
DNL errors to show the deviation of the real transfer curve from
the ideal one.
A system will clock the MP8799 continuously or it will give
clock pulses intermittently when a conversion is desired. The
timing of Figure 8a shows normal operation, while the timing of
Figure8bkeepstheMP8799inbalanceandreadytosamplethe
analog input.
After a tester has measured all the transition voltages, the
computer draws a line parallel to the ideal transfer line. By defi-
nition the best fit line makes equal the positive and the negative
INL errors. For example, an INL error of –1 to +2 LSB’s relative
to the Ideal Line would be +1.5 LSB’s relative to the best fit line.
CLOCK
DATA
N
N+1
N
N+1
a. Continuous sampling
Output
Codes
Best Fit Line
7
CLOCK
DATA
N
BALANCE
N
Real Transfer Line
6
5
b. Single sampling
EFS
INL
4
Figure 8. Relationship of Data to Clock
Analog Input
Ideal Transfer Line
3
2
1
The MP8799 has very flexible input range characteristics.
The user may set VREF(+) and VREF(–) to two fixed voltages and
then vary the input DC and AC levels to match the VREF range.
Another method is to first design the analog input circuitry and
then adjust the reference voltages for the analog input range.
One advantage is that this approach may eliminate the need for
external gain and offset adjust circuitry which may be required
by fixed input range A/Ds.
LSB
Analog Input (Volt)
EZS
Figure 7. INL Error Calculation
The MP8799’s performance is optimized by using analog in-
put circuitry that is capable of driving the AIN input. Figure 9.
shows the equivalent circuit for AIN.
Clock and Conversion Timing
40 Ω
87 pF
60 pF
AV
DD
φS
R Series
40
R MUX
500
87 pF
4
160 Ω
A
IN
1 pF
10 pF
15 pF
φS
φB
+
8
1/2 [ VREF(+)
+ VREF(–) ]
300 Ω
4 pF
Channel
Selection
Control
Figure 9. Analog Input Equivalent Circuit
Rev. 3.00
8
EXAR [ EXAR CORPORATION ]
