MP8799
t
S
CLOCK
SAMPLE
N–1
AUTO
BALANCE
SAMPLE
N
AUTO
BALANCE
SAMPLE
N+1
t
R
t
B
t
F
V
IH
V
IL
when
φ
S
disconnects the latches from the comparators. This de-
lay is called aperture delay (t
AP
).
The coarse comparators make the first pass conversion and
selects a ladder range for the fine comparators. The fine compa-
rators are connected to the selected range during the next
φ
B
phase.
ANALOG
INPUT
V
OH
DATA
V
OL
T
S
V
IN
φ
S
φ
B
φ
S
Latch
V
TAP
N-1
t
DL
t
HLD
Ref
Ladder
φ
B
φ
S
COARSE COMPARATOR
φ
S
φ
B
Latch
Figure 1. MP8799 Timing Diagram
V
IN
V
TAP
THEORY OF OPERATION
Analog-to-Digital Conversion
The MP8799 converts analog voltages into 1024 digital
codes by encoding the outputs of 15 coarse and 67 fine compa-
rators. Digital logic is used to generate the overflow bit. The con-
version is synchronous with the clock and it is accomplished in 2
clock periods.
The reference resistance ladder is a series of 1025 resistors.
The first and the last resistor of the ladder are half the value of
the others so that the following relations apply:
R
REF
= 1024
∗
R
V
REF
= V
REF(+)
– V
REF(–)
= 1024
∗
LSB
The clock signal generates the two internal phases,
φ
B
(CLK
high) and
φ
S
(CLK low = sample) (See
Figure 2.).
The rising
edge of the CLK input marks the end of the sampling phase (
φ
S
).
Internal delay of the clock circuitry will delay the actual instant
Selected
Range
φ
B
FINE COMPARATOR
Figure 2. MP8799 Comparators
A
IN
Sampling, Ladder Sampling, and Conversion Timing
Figure 3.
shows this relationship as a timing chart. A
IN
sam-
pling, ladder sampling and output data relationships are shown
for the general case where the levels which drive the ladder
need to change for each sampled A
IN
time point. The ladder is
referenced for both last A
IN
sample and next A
IN
sample at the
same time. If the ladder’s levels change by more than 1 LSB,
one of the samples must be discarded. Also note that the clock
low period for the discarded A
IN
can be reduced to the minimum
t
S
time of 150 ns.
Hold Reference Value Past
Clock Change for
t
AP
Time
Short Cycle Sample will be discarded
t
S
External
Update
References
Clock
Internal
A
IN
Sample
Window
Ladder Sample
Window (MSB Bank)
Ladder Compare
(LSB Bank)
External
DATA
Settle by Clock Update Time
Reference Stable Time – For Sample A
IN
2
Reference Stable Time – For Sample A
IN
1
A
IN
X1
Sample A
IN
1
Sample A
IN
2
F
B
A
IN
X0
Sample Ladder
for A
IN
1
F
S
Sample A
IN
1
F
B
Not Used
F
S
F
B
F
S
Sample A
IN
2
A
IN
X1
Sample Ladder
for A
IN
X1
Sample Ladder
for A
IN
2
Sample Ladder
for A
IN
X2
Compare Ladder
V/S A
IN
X0
Compare Ladder
V/S A
IN
1
Compare Ladder
V/S A
IN
X1
Compare Ladder
V/S A
IN
2
DATA A
IN
0
DATA A
IN
X0
Not Used
DATA A
IN
1
DATA A
IN
X1
Not Used
Figure 3. A
IN
Sampling, Ladder Sampling & Conversion Timing
Rev. 3.00
6
EXAR [ EXAR CORPORATION ]
