MP7612
The MP7612 is equipped with a serial data (3-wire standard)
µ
-processor logic interface to reduce pin count, package size,
and board wire (space). If the LD signal is high, the CLK signal
loads the digital input bits (SDI) into the shift register (4 bits ad-
dress A3 to A0 plus 12 bits data DB11 to DB0 for the MP7612).
The LD signal going low loads the data into the selected DAC.
Function
Shift Data In
and Out
Stop Shifting
Data In and
Out
Load DACs
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
A3
X
X
A2 A1 A0
X
X
X
X
X
X
LD
1
0
The LD signal going low also disables the serial data (SDI), out-
put (SDO 3-stated) and the CLK input. This design tremen-
dously reduces digital noise and glitch transients into the DACs
due to free running CLK and SDI. Note also that the preset sig-
nal (RST) resets all analog outputs to 0 volt regardless of digital
inputs.
CLK
0
→
1
Repeat
RST
1
1
SDI
Data Input
Valid
X
SDO
Data Output
Valid
Hi-Z
X
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No Operation
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
No Operation
No Operation
No Operation
X
1
1
Reset all DACs
to 0 V
X
1
1
X
1
1
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
X
X
X
Hi-Z
Hi-Z
X
Table 1. Digital Function Truth Table
Serial In/Serial Out
Note: For timing information see Electrical Characteristics
Rev. 3.00
8
EXAR [ EXAR CORPORATION ]
