MP7612
MSB
D11
1
SDI
A3
A2
A1
A0
D10
D9
D8
D7
D6
D0
(Data In) 0
1
CLK
0
1
LD
0
DAC Register
Loaded
1
SDO
0
A3 (1)
Previous Data
V
OUT
Notes:
(1) Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to
complete the readback.
Figure 1. Serial Data Timing and Loading
t
DS
1
0
SDI
t
t
DH
t
HZ1
HZ2
1
0
HIGH Z
SDO
CLK
LD
t
LDCK
t
t
t
PD
LDSU
CH
1
0
t
CKLD2
t
t
CL
CKLD1
1
0
t
LD
+FS
–FS
V
OUT
t
SD
+1/2 LSB Band
Notes:
(1) CLK should be high during the falling edge of LD to insure proper function of the shift register.
Figure 2. Serial Data Input Timing (RST = “1”)
t
PR
1
0
RST
V
OUT
V
OUT
= 0 V
Note: Reset settling time is <t
+1/2 LSB Error Band
SD
Figure 3. Reset Operation
Rev. 3.00
7
EXAR [ EXAR CORPORATION ]
