MP7610 参数 Datasheet PDF下载

MP7610

SDI 1

(Data In) 0

CLK

1

0

1

0

1

0

Previous Data

DAC Register

Loaded

A3 (1)

MSB

A3

A2

A1

A0

D13

D12

D11

D10

D9

D8

D0

LD

SDO

V

OUT

Note:

(1)

Because A3 is available immediately after 18th clock edge of DATA Shift-in, only 17 clock cycles are

needed to complete the readback.

Figure 1. Serial Data Timing and Loading

SDI

1

0

1

0

1

0

1

0

t

CH

t

DS

t

DH

t

HZ1

SDO

t

HZ2

HIGH Z

t

LDCK2

t

PD

t

CKLD2

t

LDSU

CLK

t

CL

t

CKLD1

LD

V

OUT

+FS

--FS

t

LD

t

SD

(1)

+2 LSB Band

Note:

CLK should be high during the falling edge of LD to insure proper function of the shift register.

Figure 2. Serial Data Input Timing (RST = “1”)

RST 1

0

V

OUT

V

OUT

= 0 V

Note: Reset settling time is <t

SD

t

PR

Figure 3. Reset Operation

Rev. 4.01

7