MP7542
ADDRESS BUS VALID
A0 - A1
CS
V
INH
V
INL
t
t
AWH
AWS1
t
t
CWH
CWS1
V
INH
V
INL
t
t
WR
AWS2
WR
t
t
t
DH
CWS2
DS
V
INH
DB3 - DB0
V
INL
DATA
BUS VALID
Figure 1. Timing Diagram
MP7542 Control Inputs
MP7542 Operation
A1
A0
CS
WR
CLR
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
1
X
1
0
0
1
1
1
1
1
1
1
1
1
Resets DAC 12-bit register to code 0000 0000 0000
No operation; device not selected
Load LOW byte data register on edges as shown
0
0
Load applicable
data register
with data at
D0 - D3
0
0
Load MIDDLE byte data register on edges as shown
Load HIGH byte data register on edges as shown
0
0
0
0
0
Load 12-bit DAC register with data in LOW byte, MIDDLE
byte, & HIGH byte data registers
NOTES
1. 1 indicates logic HIGH
2. 0 indicates logic LOW
3. X indicates don’t care
4.
indicates LOW to HIGH transition
5. MSB XXXX XXXX XXXX LSB
high
byte
middle low
byte byte
6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable.
Table 1. Truth Table
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
