MP7542
ORDERING INFORMATION
Package
Type
Temperature
INL
(LSB)
DNL
(LSB)
Gain Error
(LSB)
Part No.
Range
–40 to +85°C
Plastic Dip
MP7542JN
+1
+2
+14.5
–40 to +85°C
–40 to +85°C
Plastic Dip
SOIC
MP7542KN
MP7542JS
+1/2
+1
+1
+2
+14.5
+14.5
–40 to +85°C
SOIC
MP7542KS
+1/2
+1
+14.5
–40 to +85°C
–40 to +85°C
–55 to +125°C
–55 to +125°C
Ceramic Dip
Ceramic Dip
Ceramic Dip
Ceramic Dip
MP7542AD
MP7542BD
MP7542SD*
MP7542TD*
+1
+1/2
+1
+2
+1
+2
+1
+14.5
+14.5
+14.5
+14.5
+1/2
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
1
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
I
R
I
I
R
FB
OUT1
FB
OUT1
2
3
4
15
14
13
V
V
V
V
OUT2
REF
OUT2
REF
AGND
DB3
DB2
DB1
DB0
CS
AGND
DB3
DD
DD
CLR
DGND
A1
A0
WR
CLR
DGND
A1
A0
WR
5
6
7
8
12
11
10
9
DB2
DB1
DB0
CS
16 Pin CDIP, PDIP (0.300”)
D16, N16
16 Pin SOIC (Jedec, 0.300”)
S16
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
PIN NO.
NAME
CS
DESCRIPTION
1
I
I
DAC current output. Normally
terminated at op amp.
8
Chip Select Input
Write Input
OUT1
9
WR
A0
2
DAC current output. Normally
terminated at ground.
OUT2
10
11
12
13
14
15
16
Address Bus Input
Address Bus Input
Digital Ground
A1
3
4
5
6
7
AGND
DB3
DB2
DB1
DB0
Analog Ground
DGND
CLR
Data Input Bit 3 (MSB)
Data Input Bit 2
Clear Input
V
DD
+5 V Supply Input
Reference Input
DAC Feedback Resistor
Data Input Bit 1
V
REF
Data Input Bit 0 (LSB)
R
FB
Rev. 2.00
2
EXAR [ EXAR CORPORATION ]
