MP7529B
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analogoutputs remain at the values corresponding to the data in
their respective latches (Hold mode).
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (Table 1.). When CS and WR
t
t
CS
CH
CS
t
AS
t
AH
DAC A/
DAC B
VALID
DAC A/
DAC B
CS
WR
DAC A
DAC B
t
WR
DS
L
L
L
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
WR
H
X
X
L
L
H
X
X
H
t
t
DH
L = Low State H = High State X = Don’t Care
DB7-DB0
VALID
NOTE:
1. Timing measured from (V + V ) /2
IH
IL
Figure 1. Write Cycle Timing Diagram
MICROPROCESSOR INTERFACE
Table 1. DAC’s Mode Selection
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
A0-A15
Address Bus
Address Bus
A8-A15
A**
A**
DAC A/DAC B
ADDRESS
DECODE
LOGIC
DAC A/DAC B
ADDRESS
DECODE
LOGIC
V
MA
DAC A
CS
CPU
8085
DAC A
CS
CPU
6800
A+1***
MP7529B*
WR
A+1***
φ2
MP7529B*
WR
DAC B
WR
ALE
DB0
DAC B
LATCH
8212
DB0
DB7
DB7
Data Bus
D0–D7
AD0–AD7
ADDR/Data Bus
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
