MP3275
+5 V
3k
+5 V
3k
DB
N
DB
N
3k
DB
N
C
L
3k
10pF
DB
N
C
L
10pF
a. High-Z to V
ON
b. High-Z to V
OL
a. V
ON
to High-Z
b. V
OL
to High-Z
Figure 3. Load Circuit for Data
Access Time Test
Figure 4. Load Circuit for
Bus Relinquish Time Test
STL, STS
C
L
DGND
Figure 5. Load Circuit for WR to STS Delay
Serial Data Output
The serial data output sequence is MSB (DB11) first to LSB
(DB0) last. The MSB (DB11) data bit appears at SDO when STS
goes low. The second most significant bit appears at SDO on
the SDC high-to-low transition next. The LSB (DB0) is present
at SDO on the 11th SDC high-to-low transition.
Further information regarding serial control and timing is
shown in
Figure 6., Table 4.
and
Table 5.
STS
For a minimum interconnect serial environment, the channel
address state can be generated in at least two ways, using an
address counter, or using an address serial to parallel converter.
WR can then be used as the counter clock or shift register load
signal as well as the A/D converter start convert signal on the ris-
ing edge. (Note that the falling edge loads the address present at
the address port.)
t
21
SDC
t
22
SDO
SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t
21
.
Rev. 4.00
9
ÇÇÇÇÇ
ÇÇÇÇÇ
See Table 4
t
20
DB10
DB11 (MSB)
Figure 6. Serial Data Mode Timing
EXAR [ EXAR CORPORATION ]
