MP3275
The MP3275 is easily interfaced to a wide variety of digital
systems. Discussion of the timing requirements of the MP3275
control signals follows.
vious conversion remains selected. In this case the track
andholdsettlingtimeisomittedandSTLnevergoeshigh. At
the rising edge of WR the input signal is sampled, and con-
version is started.
Figure 1. shows a complete timing diagram for the MP3275
convert start operation.
There are two possible states that the data output could be in
during a conversion.
WR is used to initiate a conversion.
1. If RD is held high during a conversion the output would re-
main high impedance throughout the conversion. This is the
preferred method of operation as any noise present on SDO
is rejected.
A conversion is started by taking WR low, then high again
(conversion is enabled on the rising edge of WR). There are two
possible conditions that will affect conversion timing.
1. ADEN = 1. At the falling edge of WR, the input channel is
determined by the data present on the address bits. The
track and hold begins to settle after which STL returns low,
indicating that the multiplexer, buffer amp, and sample/hold
have settled to less than 1/2 LSB of final value. If the rising
edge of WR returns high prior to STL going low, conversion
will begin on the falling edge of STL. If the rising edge of WR
is delayed until after STL returns low, the input signal is sam-
pled and the conversion is started at the rising edge of WR
giving the user better control of the sampling time.
2. If RD is held low during a conversion, the data present SDO
willbefromthepreviousconversionuntilthepresentconver-
sion is completed, when STS returns low. The data from the
new conversion will be available through SDO. The state of
RD should not change during a conversion.
Once a conversion is started and the STL or STS line goes
high, convert start commands will be ignored until the conver-
sion cycle is completed. The SDO output buffer cannot be en-
abled during conversion. In addition, all input and output
changes during conversion can introduce noise, and should be
avoided when possible.
2. ADEN = 0. At the falling edge of WR the data present at the
address is ignored and the channel selected during the pre-
Time
Interval
Tmin to
Tmax
Comments/Test Conditions
Limits
25°C
ADC Write Timing
ADC Control Timing
Address to WR Set-Up Time
Address to WR Hold Time
WR Pulse Width
t3
t4
t5
t6
0
0
80
0
0
80
0
ns min
ns min
ns min
ns min
ADEN to WR Set-Up Time
ADC Conversion Timing
WR to STL ↑ Delay
t7
150
150
ns max
Load ckt of Figure 5, CL = 20 pF,
ADEN = 1
STL High (Settling Period)
t8
t9
t12
t10
t13
t14
10
15
200
15
150
50
15
20
250
20
150
50
µs max
µs max
ns max
µs max
ns max
ns max
Load ckt of Figure 5, CL = 20 pF
Load ckt of Figure 5, CL = 20 pF
STL = 0 when ADEN = 0
STL to STS Low (Converting)
WR to STS High (ADEN = 0)
WR to STS Low (ADEN = 1)
STS High to SDO Relinquish Time
STS Low to Data Valid (RD = 0)
Load ckt of Figure 4
Load ckt of Figure 3, CL = 20 pF
Table 2. ADC Write Timing
(See Figure 1.)
Rev. 4.00
7
EXAR [ EXAR CORPORATION ]
