XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
Name
Pin Number
37,31, 26,20
Description
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching
node at the junction between the two external power MOSFETs and the inductor. These
pins are also used to measure voltage drop across bottom MOSFETs in order to provide
output current information to the control engine.
High side driver supply pin(s). Connect BST to the external capacitor as shown in the
Typical Application Circuit on page 2. The high side driver is connected between the
BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each
cycle.
These pins can be configured as inputs or outputs to implement custom flags, power
good signals, enable/disable controls and synchronization to an external clock.
Open drain, these pins can be
on and off, shedding the load
configures as standard logic
configured, but as open drains
used to control external power MOSFETs to switch loads
for fine grained power management. They can also be
outputs or inputs just as any of the GPIOs can be
require an external pull-up when configured as outputs.
LX1-LX4
BST1-BST4
35,29, 24,18
GPI0-GPIO1
9,10
PSIO0-PSIO2
SDA, SCL
VOUT1-VOUT4
LDO5
LDO3_3
ENABLE
13,14,15
11,12
5,6,7,8
44
1
40
SMBus/I
2
C serial interface communication pins.
Connect to the output of the corresponding power stage. The output is sampled at least
once every switching cycle
Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of
the IC is in shutdown. This LDO is also used to power the internal Analog Blocks.
Output of the 3.3V standby LDO. This is a micro power LDO that can remain active
while the rest of the IC is in shutdown.
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,
registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be
placed into shutdown.
Input from the 15V output created by the external boost supply. When this pin goes
below a pre-defined threshold, a pulse is created on the low side drive to charge this
output back to the original level. If not used, this pin should be connected to GND.
Digital ground pin. This is the logic ground connection, and should be connected to the
ground plane close to the PAD.
Connect to a 2.2nF capacitor to GND.
External 5V that can be provided. If one of the output channels is configured for 5V,
then this voltage can be fed back to this pin for reduced operating current of the chip
and improved efficiency.
Output of the internal 1.8V LDO.
AVDD and AGND close to the chip.
A decoupling capacitor should be placed between
Connect
BFB
DGND
CPLL
V5EXT
AVDD
PAD
42
17
3
43
4
45
This is the die attach paddle, which is exposed on the bottom of the part.
externally to the ground plane.
ORDERING INFORMATION
Part Number
XRP7724ILB-F
Temperature
Range
Marking
Package
Packing
Quantity
Note 1
I
2
C Default
Address
Bulk
Halogen Free
-40°C≤T
J
≤+125°C XRP7724ILB
0x28 (7Bit)
44-pin TQFN
YYWW X
Halogen Free
XRP7724ILBTR-F
2.5K/Tape & Reel
-40°C≤T
J
≤+125°C
Evaluation kit includes XRP7724EVB-DEMO-1 Evaluation Board with Power
XRP7724EVB-DEMO-2P-KIT
Architect software and XRP77XXEVB-XCM (USB to I
2
C Exar Configuration Module)
“YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable.
© 2012 Exar Corporation
9/29
Rev. 1.0.1
EXAR [ EXAR CORPORATION ]
