CLC1007, CLC2007, CLC4007
For a given load capacitance, adjust R to optimize the
S
tradeoff between settling time and bandwidth. In general,
reducing R will increase bandwidth at the expense of
S
additional overshoot and ringing.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
ꢀ■
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
ꢀ■
Place the 6.8µF capacitor within 0.75 inches of the power pin
ꢀ■
Place the 0.1µF capacitor within 0.1 inches of the power pin
ꢀ■
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
ꢀ■
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Figure 8. CEB002 & CEB003 Schematic
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
Products
CLC1007 in TSOT
CEB003
CLC1007 in SOIC
CLC2007 in SOIC
CLC2007 in MSOP
CLC4007 in SOIC
CLC4007 in TSSOP
CEB006
CEB010
CEB018
CEB019
Evaluation Board Schematics
Figure 9. CEB002 Top View
Evaluation board schematics and layouts are shown in
Figures 8-20. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
© 2007-2014 Exar Corporation
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exar.com/CLC1007
Rev 1D
EXAR [ EXAR CORPORATION ]
