CLC1007, CLC2007, CLC4007
Power Dissipation
Assuming the load is referenced in the middle of the power
rails or V
/2.
supply
Power dissipation should not be a factor when operating
under the stated 2kΩ load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
The CLC1007 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 6
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
2.5
Maximum power levels are set by the absolute maximum
junction rating of 170°C. To calculate the junction
TSSOP-14
2
temperature, the package thermal resistance value Theta
(θ ) is used along with the total die power dissipation.
JA
JA
SOIC-14
1.5
SOIC-8
T
= T
+ (θ × P )
Ambient JA D
Junction
1
Where T
is the temperature of the working
Ambient
environment.
0.5
In order to determine P , the power dissipated in the load
D
TSOT-5
MSOP-8
needs to be subtracted from the total power delivered by the
supplies.
0
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
P = P
- P
load
D
supply
Figure 6. Maximum Power Derating
Supply power is calculated by the standard power equation.
P
supply
= V
× I
supply RMSsupply
Driving Capacitive Loads
V
= V - V
S+ S-
supply
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
Power delivered to a purely resistive load is:
possible unstable behavior. Use a series resistance, R ,
S
2
P
load
= ((V
)
)/Rload
eff
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 7.
load RMS
The effective load resistor (Rload ) will need to include the
eff
effect of the feedback network. For instance,
Rload in Figure 3 would be calculated as:
Input
+
-
eff
Rs
Output
R || (R + R )
L
f
g
CL
RL
Rf
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Rg
Here, P can be found from
Figure 7. Addition of R for Driving Capacitive Loads
D
S
Table 1 provides the recommended R for various capacitive
P = P
D
+ P
- P
S
Quiescent
Dynamic load
loads. The recommended R values result in approximately
<1dB peaking in the frequency response.
S
Quiescent power can be derived from the specified I values
S
along with known supply voltage, V
. Load power can
supply
be calculated as above with the desired signal amplitudes
using:
CL (pF)
RS (Ω)
-3dB BW (MHz)
(V
)
= V
/ √2
peak
load RMS
22pF
47pF
0
118
112
91
( I
)
= ( V
)
/ Rload
eff
load RMS
load RMS
15
15
6.5
100pF
492pF
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
59
P
= (V - V
)
× ( I )
load RMS
Dynamic
S+
load RMS
Table 1: Recommended R vs. C
S
L
© 2007-2014 Exar Corporation
18 / 27
exar.com/CLC1007
Rev 1D
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