CLC1005, CLC1015, CLC2005
Layout Considerations
1.5
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
SOIC-8
1
TSOT-6
ꢀ■
Include 6.8µF and 0.1µF ceramic capacitors for power supply
MSOP-8
decoupling
0.5
TSOT-5
ꢀ■
Place the 6.8µF capacitor within 0.75 inches of the power pin
ꢀ■
Place the 0.1µF capacitor within 0.1 inches of the power pin
ꢀ■
Remove the ground plane under and around the part,
0
especially near the input and output pins to reduce parasitic
capacitance
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
ꢀ■
Minimize all trace lengths to reduce series inductances
Figure 7. Maximum Power Derating
Refer to the evaluation board layouts below for more
information.
Driving Capacitive Loads
Evaluation Board Information
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
The following evaluation boards are available to aid in the
testing and layout of these devices:
possible unstable behavior. Use a series resistance, R ,
S
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 8.
Evaluation Board #
CEB002
Products
CLC1005 and CLC1015 in TSOT
CLC1005 in SOIC
Input
+
-
Rs
CEB003
Output
CEB006
CLC2005 in SOIC
CL
RL
Rf
CEB010
CLC2005 in MSOP
Rg
Evaluation Board Schematics
Figure 8. Addition of R for Driving Capacitive Loads
S
Evaluation board schematics and layouts are shown in
Figures 9-18. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
Table 1 provides the recommended R for various capacitive
S
loads. The recommended R values result in approximately
S
<1dB peaking in the frequency response.
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
CL (pF)
RS (Ω)
-3dB BW (MHz)
22pF
47pF
0
118
112
91
15
15
6.5
100pF
492pF
59
Table 1: Recommended R vs. C
S
L
For a given load capacitance, adjust R to optimize the
S
tradeoff between settling time and bandwidth. In general,
reducing R will increase bandwidth at the expense of
S
additional overshoot and ringing.
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exar.com/CLC1005
Rev 2D
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