XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
PIN ASSIGNMENT
GL_RTN1
VCCD1-2
ENABLE
V5EXT
LDO5
BST1
VCC
GH1
BFB
GL1
LX1
44
1
2
3
4
5
6
7
8
9
43
42
41
40
39
38
37
36
35
34
33
32
31
30
LDO3_3
GL_RTN2
AGND
GL2
CPLL
LX2
AVDD
GH2
VOUT1
VOUT2
XRP7724
TQFN
7mm X 7mm
29
28
27
26
25
BST2
GL_RTN3
VOUT3
GL3
VOUT4
LX3
GPIO0
GH3
Exposed Pad: AGND
GPIO1
10
11
24
23
BST3
SDA
VCCD3-4
12
SCL
13
PSIO0
Fig. 4: XRP7724 Pin Assignment
14
PSIO1
15
PSIO2
16
DVDD
17
DGND
18
BST4
19
GH4
20
LX4
21
GL4
22
GL_RTN4
PIN DESCRIPTION
Name
VCC
DVDD
Pin Number
41
16
Description
Input voltage. Place a decoupling capacitor close to the controller IC. This input is used
in UVLO fault generation.
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling
capacitor close to the controller IC.
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail(for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch.
Analog ground pin. This is the small signal ground connection.
Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
VCCD1-2
VCCD3-4
23,34
AGND
GL_RTN1-4
GL1-GL4
GH1-GH4
2
39,33, 28,22
38,32, 27,21
36,30, 25,19
© 2012 Exar Corporation
8/29
Rev. 1.0.1
EXAR [ EXAR CORPORATION ]
