7.5.2
Uncorrectable Error Status Register
The Uncorrectable Error Status register indicates error detection status of individual errors
on a 820x device. An individual error status bit that is set indicates that a particular error
was detected; software may clear an error status by writing a one to the respective bit.
Offset
x‘0104’
Field Name
Description
820x
Bits
31:21
20
Type
RO
Value
Reserved
0
0
0
0
0
0
0
0
Reserved.
REQ_ERR_STAT
ECRC_ERR_STAT
TLP_STAT
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
Unsupported Request Error Status.
ECRC Error Status (Optional).
Malformed TLP Status.
19
18
RV_OVF_STAT
CMPL_STAT
17
Receiver Overflow Status (Optional).
Unexpected Completion Status.
Completer Abort Status (Optional).
Completion Timeout Status.
16
CMPL_ABORT_STAT
CMPL_TMOUT_STAT
FC_ERR_STAT
15
14
Flow Control Protocol Error Status
(Optional).
13
RW1CS
0
POIS_TLP_STAT
Reserved
12
11:6
5
RW1CS
RO
0
0
0
0
0
0
Poisoned TLP Status.
Reserved.
DWN_ERR_STAT
DLNK_PROT_STAT
Reserved
RW1CS
RW1CS
RO
Surprise Down Error Status (Optional).
Data Link Protocol Error Status.
Reserved.
4
3:1
0
UNDEF
RO
Undefined.
820x – Data Sheet, DS-0157-D
Page238
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EXAR [ EXAR CORPORATION ]
